the timerunner is an analog clock divider and programmable pattern generator. it utilizes a voltage controlled dual logic core to create a wide range of programmable gate patterns. the timerunner starts with a
single clock source and divides it down into four individual channels. the output of each channel is based on a complex relationship between the clock source, a clock divider, and a chain of switchable and
voltage controlled logic options. the result is a unique and extremely musical patten generator.
a reimagining of the timetable
the timerunner was not designed to be a timetable 2. the timetable module was built around the concept of controllable logic and the timerunner expands on that idea in a whole new way. the timerunner builds on
the legacy of the timetable by offering more complex logic routing, better control options, and more musical results.
how it works
the signal path of the timerunner starts with an internal or external clock source. the clock is split using a divider into 4 cascading channels creating even /2, /4, /8, /16 divisions of the clock source. the
output of each channel division is then split and sent to the first logic input of both an and and xor logic chip. the second input of the and and xor logic chips is referred to as the seed. the first channel
seed is always high unless the seed input jack is used. the seed input for the remaining channels is derived from either the and or xor logic output of the previous channel using the channel seed switch. the
output of each channel is selectable between the and and xor logic output using the logic selector switch or logic in gate input.
logic selector switch and logic in gate input are at the end of the channel signal patch. their settings affect only the output of their specific channel.
the channel seed switch is at the beginning of the channel signal patch. its setting affects the output of its specific channel and also cascades to affect the channels below. for example flipping the channel
seed switch on channel 2 will affect the pattern of channel 2, channel 3, and channel 4. flipping the channel seed switch on channel 3 will affect the pattern of channel 3 and channel 4. because channel 4 is the
last channel, flipping the channel seed switch on channel 4 will affect the pattern of channel 4. the seed input of channel 1 works in the same way. if the channel 1 seed input jack is used, the result will
affect all 4 channels.
a simple example
the most basic setup uses all the channel seed and logic selector switches set in the and position. this produces a basic clock divider output. channel 1 output divides the clock by 2. channel 2 output divides
the clock by 4. channel 3 output divides the clock by 8. channel 4 output divides the clock by 16. clocking this basic setup using an audio rate oscillator turns the timerunner into a 4 octave output sub-octave
generator. flipping the channel 1 logic selector switch flips the output of channel 1 to odd beats.
timerunner controls:
clock controls:
clock rate - sets the rate of the clock lfo.
sqr out - square wave output of clock lfo.
sqr out - square wave output of clock lfo.
internal clock led - shows the logic state of the internal input.
seed logic led - shows the logic state of the seed input.
external clock led - shows the logic state of the external input.
clock in - replaces the internal lfo as the clock source.
reset in - resets the internal clock divider.
channel 1 controls:
seed in - gate input used to set the logic state of channel 1 seed. if not patched, channel 1 seed logic state is always high.
logic selector switch - selects the logic sent to the output jack of channel 1.
logic in gate input - active when logic selector switch is set to and, the logic in gate input determines the logic sent to the output of channel 1. if the gate input is high, logic is set to and. if gate input
is low, logic is set to xor.
selected logic led - yellow led used to show the active logic state for channel 1. on represents and, off represents xor.
channel 2 controls:
channel seed switch - selects the logic from channel 1 used as the seed input of channel 2.
logic selector switch - selects the logic sent to the output jack of channel 2.
logic in gate input - active when logic selector switch is set to and, the logic in gate input determines the logic sent to the output of channel 2. if the gate input is high, logic is set to and. if gate input
is low, logic is set to xor.
selected logic led - yellow led used to show the active logic state for channel 2. on represents and, off represents xor.
channel 3 controls:
channel seed switch - selects the logic from channel 2 used as the seed input of channel 3.
logic selector switch - selects the logic sent to the output jack of channel 3.
logic in gate input - active when logic selector switch is set to and, the logic in gate input determines the logic sent to the output of channel 3. if the gate input is high, logic is set to and. if gate input
is low, logic is set to xor.
selected logic led - yellow led used to show the active logic state for channel 3. on represents and, off represents xor.
channel 4 controls:
channel seed switch - selects the logic from channel 3 used as the seed input of channel 4.
logic selector switch - selects the logic sent to the output jack of channel 4.
logic in gate input - active when logic selector switch is set to and, the logic in gate input determines the logic sent to the output of channel 4. if the gate input is high, logic is set to and. if gate input
is low, logic is set to xor.
selected logic led - yellow led used to show the active logic state for channel 4. on represents and, off represents xor.
size: 12hp
module depth with ribbon cable attached: 36.5mm
power usage: 45ma
